ZMK_ECC_EN=ZMK_ECC_EN_0, MASTER_KEY_SEL=MASTER_KEY_SEL_0, ZMK_HWP=ZMK_HWP_0, ZMK_VAL=ZMK_VAL_0
SNVS_LP Master Key Control Register
| MASTER_KEY_SEL | Master Key Select These bits select the SNVS Master Key output when Master Key Select bits are enabled by MKS_EN bit in the HPCOMR 0 (MASTER_KEY_SEL_0): Select one time programmable master key. 2 (MASTER_KEY_SEL_2): Select zeroizable master key when MKS_EN bit is set . 3 (MASTER_KEY_SEL_3): Select combined master key when MKS_EN bit is set . |
| ZMK_HWP | Zeroizable Master Key hardware Programming mode When set, only the hardware key programming mechanism can set the ZMK and software cannot read it 0 (ZMK_HWP_0): ZMK is in the software programming mode. 1 (ZMK_HWP_1): ZMK is in the hardware programming mode. |
| ZMK_VAL | Zeroizable Master Key Valid When set, the ZMK value can be selected by the master key control block for use by cryptographic modules 0 (ZMK_VAL_0): ZMK is not valid. 1 (ZMK_VAL_1): ZMK is valid. |
| ZMK_ECC_EN | Zeroizable Master Key Error Correcting Code Check Enable Writing one to this field automatically calculates and sets the ZMK ECC value in the ZMK_ECC_VALUE field of this register 0 (ZMK_ECC_EN_0): ZMK ECC check is disabled. 1 (ZMK_ECC_EN_1): ZMK ECC check is enabled. |
| ZMK_ECC_VALUE | Zeroizable Master Key Error Correcting Code Value This field is automatically calculated and set when one is written into ZMK_ECC_EN bit of this register |